Mindlance
Engineering - Verification Engineer 4
Austin, Texas, US
Role snapshot
Mindlance is hiring a Engineering - Verification Engineer 4 on a full-time basis. This is a role based in Austin, Texas, US.
- Company
- Mindlance
- Location
- Austin, Texas, US
- Job type
- Full-time
- Posted
- Nov 6, 2026
Who this role suits
The listing does not state a required experience level here. Read the requirements in the description below and apply if they match your background.
How to prepare your application
- Match your résumé to the requirements in the description, using the same wording where it is honest to do so.
- Prepare a short example for each requirement you meet, and be ready to explain any you only partly meet.
- Read what Mindlance publishes about its product or team, so you can say clearly why this role and this company.
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About the role
Job Description
Job Description
PREFERRED EXPERIENCE:
Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence)
Strong proficiency in System Verilog Assertions (SVA) and formal property specification
Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
Familiarity with scripting languages (TCL, Python, Perl) for flow automation
Extensive experience in design verification with a strong focus on formal verification
Expertise in System Verilog and UVM-based verification methodologies - Nice to have